笔记6-vivado中clock 的IP -差分晶振输入使用

  1 `timescale 1ns / 1ps
  2 //////////////////////////////////////////////////////////////////////////////////
  3 // Company: 
  4 // Engineer: 
  5 // 
  6 // Create Date: 2023/09/08 22:19:01
  7 // Design Name: 
  8 // Module Name: led_2
  9 // Project Name: 
 10 // Target Devices: 
 11 // Tool Versions: 
 12 // Description: 
 13 // 
 14 // Dependencies: 
 15 // 
 16 // Revision:
 17 // Revision 0.01 - File Created
 18 // Additional Comments:
 19 // 
 20 //////////////////////////////////////////////////////////////////////////////////
 21 
 22 
 23 module led_2(
 24                 sys_clk_p                       ,
 25                 sys_clk_n                       ,
 26                 rst_n                           ,
 27                 clk_out_25m                     ,
 28                 clk_out_50m                     ,
 29                 clk_out_100m                    ,
 30                 clk_out_200m                    ,
 31                 clk_out_300m                    ,
 32                 led_out     
 33     );
 34 parameter               T_40ms  = 24'd10_000_000;
 35    
 36 input                   sys_clk_p               ;
 37 input                   sys_clk_n               ;   
 38 input                   rst_n                   ;    
 39 output                  clk_out_25m             ;
 40 output                  clk_out_50m             ;
 41 output                  clk_out_100m            ;
 42 output                  clk_out_200m            ;
 43 output                  clk_out_300m            ;
 44 output  [3-1 :0]        led_out                 ;
 45 
 46 reg     [3-1 :0]        led_out                 ;
 47 reg     [24-1:0]        cnt0                    ;
 48 
 49 wire                    clk_50m                 ;
 50 wire                    add_cnt0                ;
 51 wire                    end_cnt0                ;
 52 wire                    locked                  ;
 53 
 54 assign clk_50m =        clk_out_50m             ;
 55 
 56 
 57 clk_wiz_0 instance_name
 58    (
 59     // Clock out ports
 60     .clk_out1_300m(clk_out_300m),     // output clk_out1_300m
 61     .clk_out2_200m(clk_out_200m),     // output clk_out2_200m
 62     .clk_out3_100m(clk_out_100m),     // output clk_out3_100m
 63     .clk_out4_50m(clk_out_50m),     // output clk_out4_50m
 64     .clk_out5_25m(clk_out_25m),     // output clk_out5_25m
 65     // Status and control signals
 66     .resetn(rst_n), // input resetn
 67     .locked(locked),       // output locked
 68    // Clock in ports
 69     .clk_in1_p(sys_clk_p),    // input clk_in1_p
 70     .clk_in1_n(sys_clk_n));    // input clk_in1_n
 71 
 72 `ifdef  ILA_LED_2
 73     ila_0   u_ila_led_2(
 74                     .clk        (clk_out_300m       ),
 75                     .probe0     (clk_out_200m       ),
 76                     .probe1     (clk_out_100m       ),
 77                     .probe2     (clk_out_50m        ),
 78                     .probe3     (clk_out_25m        ),
 79                     .probe4     (locked             )
 80     );
 81 `endif
 82    
 83 always@(posedge clk_50m or negedge rst_n)begin
 84     if(!rst_n)begin
 85         cnt0 <= 0;
 86     end
 87     else if(add_cnt0)begin
 88         if(end_cnt0)begin
 89             cnt0 <= 0;
 90         end
 91         else begin
 92             cnt0 <= cnt0 + 1'b1;
 93         end
 94     end
 95 end
 96 
 97 assign add_cnt0 = 1;
 98 assign end_cnt0 = add_cnt0 && cnt0 == T_40ms - 1;
 99 
100 always@(posedge clk_50m or negedge rst_n)begin
101     if(!rst_n)begin
102         led_out <= 3'b001;
103     end
104     else if(end_cnt0)begin
105         led_out <= {led_out[1:0],led_out[2]};
106     end
107 end
108 
109 
110 
111 
112 endmodule