AHB Matrix项目理解--框架理解与关键代码

virtual task do_init_write(REQ t);
    wait_for_bus_grant();      //第一个周期的上升沿
    vif.cb_mst.htrans <= NSEQ;
    vif.cb_mst.haddr  <= t.addr;
    vif.cb_mst.hburst <= t.burst_type;
    vif.cb_mst.hsize  <= t.burst_size;
    vif.cb_mst.hwrite <= 1'b1;
    @(vif.cb_mst);             //第一个周期的下降沿
    if(t.burst_type == SINGLE) begin
      _do_drive_idle();
    end
    vif.cb_mst.hwdata <= t.data[0];
    // check ready with delay in current cycle
    forever begin
      @(negedge vif.hclk);     //第二个周期的下降沿
      if(vif.hready === 1'b1) begin
        break;
      end
      else
        @(vif.cb_mst);
    end

    // update current trans status
    t.trans_type = NSEQ;
    t.current_data_beat_num = 0; // start beat from 0 to make consistence with data array index
    t.all_beat_response[t.current_data_beat_num] = response_type_enum'(vif.hresp);
  endtask

virtual task wait_for_bus_grant();
    @(vif.cb_mst iff vif.cb_mst.hgrant === 1'b1);
  endtask
```

`ifndef user_lvc_ahb_master_monitor
`define user_lvc_ahb_master_monitor

class user_lvc_ahb_master_monitor extends lvc_ahb_monitor;//为什么继承于LVC_AHB_master_MONITOR?见obsidian

  `uvm_component_utils(user_lvc_ahb_master_monitor)

  function new(string name = "user_lvc_ahb_master_monitor", uvm_component parent = null);
    super.new(name, parent);
  endfunction

  task collect_transfer(output lvc_ahb_transaction t);
    // collect transfer from interface
    t = lvc_ahb_transaction::type_id::create("t");
    wait(vif.htrans == NSEQ); #1ps;  //不用clocking，就在当前一拍采样。第一拍地址周期的下降沿前面一点点

    t.trans_type = trans_type_enum'(vif.htrans);
    t.xact_type = xact_type_enum'(vif.hwrite);
    t.burst_type = burst_type_enum'(vif.hburst);
    t.burst_size = burst_size_enum'(vif.hsize);
    t.addr = vif.haddr;
    forever begin
      monitor_valid_data(t);
      if(t.trans_type == IDLE) 
        break;
    end
    t.response_type = t.all_beat_response[t.current_data_beat_num];
  endtask

  task monitor_valid_data(lvc_ahb_transaction t);

    @(vif.cb_mon); #1ps;          //第二拍数据周期的上升沿往后一点点
    wait(vif.hready === 1); #1ps; //第二拍的下降沿之前
    
    //在后面添加1ps，可以保证检测到的数据避免delta cycle的问题

    //当前这一拍去检查hready信号，此时monitor能跟上driver

    //因为driver是第二拍的下降沿附近，现在的monitor检查的也是第二拍的下降沿附近,细致来说，monitor获取数据在driver之前
    //monitor得到数据就是要在driver返回rsp之前啊，不然rgm的内建序列测试会报错的  //这句话重中之重
    //monitor要先拿到数据返回给寄存器模型更新镜像值       //这句话也是重中之重

    t.increase_data();
    t.current_data_beat_num = t.data.size() - 1;
    // get draft data from bus 
    t.data[t.current_data_beat_num] = t.xact_type == WRITE ? vif.hwdata : vif.hrdata;
    // NOTE:: alinged not to extract the valid data after shifted
    // extract_vali_data(t.data[t.current_data_beat_num], t.addr, t.burst_size);
    t.all_beat_response[t.current_data_beat_num] = response_type_enum'(vif.hresp);
    t.trans_type = trans_type_enum'(vif.htrans);
  endtask

endclass

`endif // LVC_AHB_MONITOR_SV

//为什么取名“ipl1”？
//VCS的设计层次rkv_ahbmtx_tb---dut(rkv_DW_ahb)---
//U_arb(rkv_DW_ahb_arb)---U_arbif(rkv_DW_ahb_arbif)
//找到reg类型的变量，ipl1对应AHB_PL1，以此类推
        this.AHB_PL1.add_hdl_path_slice("ipl1",0,32);
        this.AHB_PL2.add_hdl_path_slice("ipl2",0,32);
        this.AHB_PL3.add_hdl_path_slice("ipl3",0,32);
        this.AHB_EBTCOUNT.add_hdl_path_slice("ebtcount",0,32);
        this.AHB_EBT_EN.add_hdl_path_slice("ebten",0,32);
        this.AHB_EBT.add_hdl_path_slice("ebt",0,32);
        this.AHB_DFLT_MASTER.add_hdl_path_slice("idef_mst",0,32);
        this.AHB_VERSION_ID.add_hdl_path_slice("iahb_version_id",0,32);
//添加前门后门访问的相对路径

`ifndef RKV_AHBMTX_REG_ACCESS_VIRT_SEQ_SV
`define RKV_AHBMTX_REG_ACCESS_VIRT_SEQ_SV

class rkv_ahbmtx_reg_access_virt_seq extends rkv_ahbmtx_base_virtual_sequence;

  `uvm_object_utils(rkv_ahbmtx_reg_access_virt_seq)
  function new (string name = "rkv_ahbmtx_reg_access_virt_seq");
    super.new(name);
  endfunction

  virtual task body();
    uvm_reg_access_seq  reg_access_seq = uvm_reg_access_seq::type_id::create("reg_access_seq");
    super.body();
    `uvm_info("body", "Entered...", UVM_LOW)
    //disable coverage model
    cfg.enable_cov = 0;
    reg_access_seq.model = rgm;
    reg_access_seq.start(null);
    foreach (rgm.maps[i]) begin
    rgm.ahbmtx.AHB_DFLT_MASTER.write(status,'h3,UVM_FRONTDOOR,rgm.maps[i]);
      rgm.ahbmtx.AHB_DFLT_MASTER.mirror(status,UVM_CHECK,UVM_BACKDOOR, uvm_reg_map::backdoor());
      //观察源代码知uvm_reg_map::backdoor()不用也没事
      // rgm.ahbmtx.AHB_DFLT_MASTER.mirror(status,UVM_CHECK,UVM_BACKDOOR);
     rgm.ahbmtx.AHB_DFLT_MASTER.write(status,'h1,UVM_BACKDOOR,rgm.maps[i]);
      rgm.ahbmtx.AHB_DFLT_MASTER.mirror(status,UVM_CHECK,UVM_FRONTDOOR,rgm.maps[i]);

    end
    //上述代码都是根据DVT里面uvm_reg_access_seq的（140-164行）源代码抄来修改的
    `uvm_info("body", "Exiting...", UVM_LOW)
  endtask
endclass
`endif

//来源于rkv_ahbmtx_cov.sv
...
function void write(lvc_ahb_transaction tr);
    logic[15:0] hbusreq_masked;
    super.write(tr);
    if(cfg.enable_cov)begin
      hbusreq_masked = vif.hbusreq & (~(16'h1 << cur_mid));
//代码的正确性：

      //左移1位后取反
      //如cur_mid = 1时，
      case(cur_acc)
        REGACC:begin:regacc_cov_collect
            case(cur_reg.get_name())
              "AHB_PL1":cgs_reg_prioX[0].sample(tr.data[0][3:0]);
              "AHB_PL2":cgs_reg_prioX[1].sample(tr.data[0][3:0]);
              "AHB_PL3":cgs_reg_prioX[2].sample(tr.data[0][3:0]);
            endcase
            if($countones(hbusreq_masked) == 0)  //满足条件，single slave（单个） 在访问
              cgs_single_slave_access_reg[cur_mid - 1].sample(1);
            if($countones(hbusreq_masked) == cfg.mst_num - 1)
              cgs_all_slaves_access_reg[cur_mid - 1].sample(1);
          end
        MEMACC:begin
            if($countones(hbusreq_masked) == 0)
              cgs_single_slave_access_mem[cur_mid - 1].sample(1);
            if($countones(hbusreq_masked) == cfg.mst_num - 1)
              cgs_all_slaves_access_mem[cur_mid - 1].sample(1);
          end
        ILLACC:begin
          cgs_illegal_addr_access[cur_mid - 1].sample(1);
        end
      endcase
    end
  endfunction
...
//

hbusreq_masked = vif.hbusreq & (~(16'h1 << cur_mid));

if($countones(hbusreq_masked) == 0)  //满足条件，single slave（单个） 在访问
              cgs_single_slave_access_reg[cur_mid - 1].sample(1);

 if($countones(hbusreq_masked) == cfg.mst_num - 1)
              cgs_all_slaves_access_reg[cur_mid - 1].sample(1);

//cov.sv中
...
forever begin :listen_to_reset_event
          realtime last_tr_time_wd;
          realtime reset_assert_time;//开始reset的时刻
          realtime next_tr_time_wd;
          @(negedge vif.rstn iff cur_tr_time != 0ns);//排除第一次的reset
          //check if last trans and next trans timing window
          reset_assert_time = $time;
          last_tr_time_wd = reset_assert_time - cur_tr_time;
          //cur_tr_time为进入write的时刻，继承于subscriber里面的变量
          fork:wait_next_trans_thread
            ahbmtx_regacc_fd_e.wait_trigger();//抄I2C的cgm 370行里面的写法
            ahbmtx_memacc_fd_e.wait_trigger();
          join_any
          disable wait_next_trans_thread;
          next_tr_time_wd = $time - reset_assert_time;//结束reset，然后开启下一trans的时刻
          if(last_tr_time_wd < 100ns && next_tr_time_wd < 100ns)
            cg_reg_hard_reset.sample(1);
        end
...

set_type_override_by_type (lvc_ahb_master_monitor::get_type(),user_lvc_ahb_master_monitor::get_type());
set_type_override_by_type (uvm_reg_bit_bash_seq::get_type(),user_uvm_reg_bit_bash_seq::get_type());